Welcome to Sarcina
Founded in 2011, Sarcina Technology is a semiconductor packaging and testing turnkey company in Palo Alto, California, with a design and supply chain management office in Taipei, Taiwan. It is led by industry veterans from companies like AT&T Bell Labs, DEC, Intel, and TSMC.
Sarcina provides leading companies with package design and power/signal integrity simulation. In addition, the company offers wafer probing and final test hardware design, test program development, and one-stop turnkey service.
Sarcina Technology works with the world's foremost foundries to ensure high quality products. It handles everything, from the simplest to the most complex packages. The results are self-evident: Since its formation, Sarcina's tape-outs have all been first-time successes.
In 2018, Sarcina expanded its package assembly and test service. Today, the company defines its business model as “wafer-in, chip-out.” Customers send Sarcina their wafers from foundries and Sarcina designs the final test and wafer sort hardware and converts DFT test patterns to ATE test vectors. Sarcina then handles all supply chain logistics.
Services Provided by Sarcina
Lower total packaging costs with Sarcina’s exclusive WIPO service. WIPO stands for wafer-in, product-out and it eliminates the exorbitant costs of maintaining a hardware team for packaging, testing, and production. WIPO covers: wafer bumping, wafer sort, package design, test hardware design, design simulations, substrate/hardware fabrication, chips assembly, chips final test, device qualification, and production.
Sarcina provides a complete semiconductor packaging service portfolio.
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Sarcina has assembled a world-class engineering team. Each one of our engineers has 10 to 25 years of industrial
experience servicing top US and Taiwan semiconductor companies before joining Sarcina.
They have experience designing hundreds of packages for worldwide customers such as DEC, Intel, Microsoft, Qualcomm, Cisco, Avago, Huawei, Infineon, NTT, and Sony.
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Sarcina has assembled a world-class engineering team. Each one of our engineers has 10 to 25 years of industrial
experience servicing top US and Taiwan semiconductor companies before joining Sarcina.
They have experience designing hundreds of packages for worldwide customers such as DEC, Intel, Microsoft, Qualcomm, Cisco, Avago, Huawei, Infineon, NTT, and Sony.
