We use commercially available software tools to convert customer-provided DFT test patterns from STIL, WGL, or EVCD file formats into functional test vectors for physical device testers. Our powerful tools allow our customer’s DFT engineers to avoid the frustration of dealing with unfamiliar simulators and tester data formats. This approach saves time and resources, and also lowers the risk of conversion errors, which would be costly to debug.
Our process also allows us to quickly evaluate customer provided DFT test patterns and to determine if the converted test vectors can be successfully accepted by a physical device tester without any format issues.
Depending on our customer’s requirements, Sarcina works with them to come up with a viable and cost effective test plan for wafer probing and final test. A typical test plan usually includes the following:
Power/Ground Open/Short (O/S) test
JTAG DC boundary scan connectivity test
DC Parameters Test
Memory BIST (MBIST) test and e-Fuse
At-speed and Stuck-at ATPG scan test for digital logic
High speed Serdes/DDR BIST
Internal parallel loopback and external serial loopback for SerDes (BIST)
DDR IO internal/external loopback for all data and address (BIST)
Room temperature test and cold/hot temperature test
Supply voltage minimum, nominal, and maximum test at different temperatures