Technology Available for Licensing

25G Serializer/Deserializer Package Design


Overview

  • Sarcina Technology LLC has created a package design method for the optimization of package differential impedance at data rates of 25 Gb/s and beyond which is disclosed in US Patent App 14/729,050.
  • The method optimizes the differential impedance of package vertical interconnections of BGA ball, via, and PTH as well as around the joint between the vertical interconnection and the horizontal interconnection of trace.
  • The invention leads to significant operational improvements and cost savings as explained herein.

Achieved Performance Improvement

      At 8ps rise time:
  • a <5% impedance variation is obtained with a 0.8 mm BGA ball pitch and a 10-layer buildup substrate.
  • a <10% impedance variation is obtained with a 1 mm BGA ball pitch and a 14-layer buildup substrate.
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