SiP and MCM
2.5D TSV OR ORGANIC SUBSTRATE?
Inside this package, there are two microprocessor dice, thirty four decoupling capacitors for core and DDR, thirty two AC coupling capacitors for SerDes, and two resistors.
Originally we planned to use 2.5D TSV technology in the package design because of the many components and high routing density.
After a feasibility study, we concluded that the organic substrate solution sufficiently accomplishes the interconnection. This approach could save our customer a sizable NRE cost in packaging and dramatically lower the unit price.
At Sarcina, we take a practical approach to our customer’s packaging request. We emphasize cost effective solutions because we want to do the best for our customer’s bottom line.
Stacked Die System-in-Package (SiP)
Substrate & Die Layer Stack-up
A product has a single ASIC die in the package. Due to PCB board space constraints, customers want to insert two additional dice into the package while keeping the package body size and BGA ball map unchanged.
Our solution was to insert the LPDDR die underneath the largest ASIC die and use the extra space under the ASIC die for wire bond.
The result is three chips merged into one. Also, the effective PCB area is shrunk by two thirds.
Five Die Stacked System-in-Package
This chip has five identical dice in a package. It has both stacked and side-by-side dice. Many customers opt to stack multiple memory dice in their package to increase memory density while conserving space. Included passive components inside the package are forty-one 0201 DDR3 termination resistors and some coupling capacitors.
A Hybrid Stacked Die System-in-Package
