Inside this package, there are two microprocessor dice, thirty four decoupling capacitors for core and DDR, thirty two AC coupling capacitors for SerDes, and two resistors.
Originally we planned to use 2.5D TSV technology in the package design because of the many components and high routing density.
After a feasibility study, we concluded that the organic substrate solution sufficiently accomplishes the interconnection. This approach could save our customer a sizable NRE cost in packaging and dramatically lower the unit price.
At Sarcina, we take a practical approach to our customer’s packaging request. We emphasize cost effective solutions because we want to do the best for our customer’s bottom line.