Teaming up with our long-time partners in Taiwan, Sarcina designs and manufactures the socket and change kit for automatic test handlers used in semiconductor final test. Leveraging our strong power integrity and signal integrity (PI/SI) simulation capability as well as our strong package and PCB design capability, Sarcina designs the loadboard for final test.
Different from pure loadboard design houses where all the PI/SI simulations are only performed on the loadboard, Sarcina’s PI/SI simulation covers the entire channel, from chip to chip including package, socket, and loadboard. Our analysis provides the real device performance under the final test environment. It helps us meet the final test requirements while lowering the hardware design NRE cost and lead time.
A quick rundown of our final test process:
Sarcina works with our external partner to develop the loadboard, socket, and change kit for each new chip design. Once a die is assembled, they enter the final test process. The chips are placed in a tray, and the change kit places each chip onto the loadboard socket and runs the final test program. Any chips that don’t pass the test are identified as electrical rejects.