We will work with you to design a cost-effective package that will also minimize the PCB cost to lower its layer count and optimize its assembly yield.

We will work with your substrate manufacturer to correct all DRC violations for high substrate yield.

We will work with your assembly house to meet all assembly rules for high assembly yield in a production environment.

As shown on the right, there are nearly one thousand bond wires in the package design. We carefully designed the four die stacked SIP package. As a result, on the initial prototyping assembly, we have already achieved a >90% assembly yield.